The invention is related to the field of processors, and more specifically to techniques for reducing memory access time in processing systems in order to improve performance.
In processing systems, it is typical to provide a processor coupled to a memory in which data used by the processor are stored. During the execution of a program, the processor accesses the memory in order to store or retrieve data. It is generally desirable that the memory have a sufficiently fast access time so that processing power is not wasted waiting for memory operations to complete. However, this goal must be balanced against other needs of the processing system. The memory also must be large enough to store sufficient data to minimize the performance impact of input/output (I/O) operations, which are extremely slow as measured in execution cycles of the processor. Also, the memory must generally be accessible to other entities, such as DMA controllers used to perform I/O operations. Memories that satisfy these other needs generally exhibit greater latency, or access time, than needed to achieve the best possible processing performance from a system.
There are known techniques for reducing the average access time of memory in a processing system. According to one technique, one or more read buffers having fast access time are placed near the processor, and are also coupled to the memory. When the processor makes a request for a word of data, a block of multiple words including the desired word is requested from memory. When the block is returned, the desired word is given to the processor, and the remainder of the block is stored in a read buffer. Subsequent processor requests for data words in the block are satisfied from the read buffer, and therefore are satisfied much more quickly than if additional requests to the system memory were required.
Although overall performance can thus be improved by using read buffers, there is still a performance limitation caused by the access time for data blocks. It would be desirable to further reduce average memory latency in order to achieve greater performance in processing systems.